1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method for fabricating an EEPROM (electrically erasable and programmable read-only memory) device with improved quality for the tunneling oxide layers therein.
2. Description of Related Art
An EEPROM (electrically erasable and programmable read-only memory, also abbreviated as E.sup.2 PROM) is a semiconductor, nonvolatile, programmable read-only memory device whose contents can be electrically erased and then selectively rewritten without having to remove it from its host circuit board. Due to the erasable and programmable feature, the EEPROM is more versatile in utilization than other types of ROMs. In the EEPROM device, the data erasure and rewrite operation can be carried out one bit at a time. A conventional single-polysilicon EEPROM device is illustratively depicted in the following with reference to FIGS. 1A-1C.
FIG. 1A shows the first step, in which a semiconductor substrate 10 is prepared. A field oxide layer 11 is then formed in a selected area. A first oxide layer 12 is subsequently formed over the entire top surface of the substrate 10 and the field oxide layer 11. The first oxide layer 12 is then selectively removed so as to form a tunneling window 13, exposing a selected area on the substrate 10. Next, a second oxide layer 14 is formed over the entire top surface of the wafer, including the entire first oxide layer 12 and filling the tunneling window 13. The part of the second oxide layer 14 that is laid in the tunneling window 13, as indicated by the reference numeral 14b, serves as a tunneling oxide layer; all the other parts of the second oxide layer 14 and its underlying first oxide layer 12 serve in combination as a gate oxide layer, here collectively indicated by the reference numeral 14a.
FIG. 1B shows the subsequent step, in which a polysilicon layer 15 and a tungsten silicide (WSi) layer 16 are successively formed over the entire top surface of the wafer through, for example, two respective chemical-vapor deposition (CVD) processes. The polysilicon layer 15 and the WSi layer 16 are then selectively removed, allowing the remaining portions of these two layers 15 and 16 that are laid over the tunneling oxide layer 14b on one side of the field oxide layer 11 to serve as a floating gate 17, while the remaining portions of the same over the gate oxide layer 14a on the other side of the field oxide layer 11 serve as a gate 18.
FIG. 1C shows the subsequent step, in which a high-voltage ion-implantation (HVI) process is performed on the wafer with the field oxide layer 11, the floating gate 17, and the gate 18 serving as a mask. A heat-treatment process is then performed on the wafer. Through these two processes, impurity ions are implanted and driven into the unmasked portions of the substrate 10 to form a pair of source/drain regions 19 in the substrate 10 on both sides of the gate 18.
In the foregoing method, the floating gate 17 is formed from a combination of the WSi layer 16 and the underlying polysilicon layer 15. Since the WSi layer 16 is customarily formed through CVD process, remnant fluorine (F) or chlorine (Cl) atoms can be left in the WSi layer 16. A bad consequence of this can occur when the WSi layer 16 is heated in the subsequent heat-treatment process used to drive ions into the source/drain regions, because stress can occur in the heated WSi and the remnant fluorine or chlorine atoms in the WSi layer 16 can be diffused into the tunneling oxide layer 14b. This turns the tunneling oxide layer 14b into a trapping center. During operation of the EEPROM device, the electric charges caught in the trapping center cause uneven and inconsistent electric fields in the tunneling oxide layer 14b, which easily causes breakdown in the tunneling oxide layer 14b. The reliability of the resultant EEPROM device is thus degraded.